1. Field of the Invention
The present invention relates to a method for forming a semiconductor thin-film, and a resulting semiconductor thin-film formed thereby.
More particularly, the present invention relates to a method for forming a semiconductor thin-film of polycrystalline silicon of a large grain size which makes feasible the production of semiconductor devices such as a thin-film transistor (TFT) and the like having a high performance.
2. Related Background Art
Regarding the technique for forming a polycrystalline silicon semiconductor thin-film of a large grain size, a method was reported in which an amorphous silicon thin-film is allowed to grow in a solid phase to form a polycrystalline silicon thin-film for use for a thin-film transistor [T. Noguchi, T. Ohshima, & T. Hayashi; Polysilicon Films and Interfaces, Boston, 1987, Mater. Res. Soc. Symp. Proc., Vol. 106, p. 293 (Elsecier Science Publishing, New York, 1988)].
The detail thereof is described below.
In this method, initially, an amorphous Si layer is formed on a substrate. The amorphous Si layer may be formed by a known method such as implantation of Si ions into a polycrystalline Si layer for amorphousness, thermal decomposition of SiH.sub.4 by chemical vapor deposition, and deposition of Si by electron-beam vapor deposition on a substrate kept at room temperature.
Subsequently, the amorphous Si layer is heat-treated at 600.degree. C. in nitrogen atmosphere for several to several ten hours. Thereby, crystal nuclei are formed in the amorphous Si layer, and the nuclei grow larger with the length of treatment time resulting finally in mutual collision of the crystal grains, forming crystal boundaries. For example, an amorphous Si layer of about 1000 .ANG. thick formed by Si ion implantation comes to have crystal grains of as large as 5 .mu.m diameter by thermal treatment at 600.degree. C. for 100 hours. A thin-film transistor formed on a polycrystalline Si layer having such a large grain diameter is observed to have a carrier mobility of more than 100 cm.sup.2 /vsec. Accordingly, this treatment is a significantly useful method for grain growth.
However, the inventors of the present invention have found the disadvantages of the above-mentioned prior art as the result of practical experiment and detailed consideration as below.
(1) An amorphous silicon layer will not crystallize at a temperature below 600.degree. C., so that the treating temperature cannot be lowered. For example, no crystal nucleus is formed by a heat treatment at 550.degree. C. for 2000 hours in the silicon layer which is kept amorphous. The temperature 600.degree. C. is generally higher than the heat resistance temperature of glass employed for amorphous Si thin-film transistors. Therefore, heat-resistant expensive quartz glass has to be used as the base material.
(2) Generally, crystallization of amorphous thin film by solid-phase crystal growth requires time of as much as multiples of ten hours from the start of heat treatment to achieve complete polycrystalline state independently of temperature. This is because the induction period from the start of the heat treatment to formation of crystal nuclei is as much as multiples of ten hours, and the growth of the crystal nuclei to crystal grain is extremely slow. For example, in amorphous Si formed by Si.sup.+ ion implantation is observed to exhibit induction period of about 10 hours at 600.degree. C., and requires long time of 100 hours from the start of the heat treatment to the completion of crystallization of the whole film.
The above two problems are serious in industrial production from the standpoint of production efficiency and production cost, which have to be solved naturally.
(3) In addition to the disadvantage of (2) above, the nucleus formation in the amorphous Si occurs at random positions, so that the grain boundaries, which are formed by mutual collision of grown crystal grains, formed at random positions, which cannot be controlled. In fact, Si.sup.+ implantation for effecting amorphousness of the polycrystalline Si layer, and subsequent heat treatment at 600.degree. C. will give a polycrystalline layer having a crystal diameter of 5 .mu.m at the most. However, the grain size distributes broadly from 1 .mu.m to 5 .mu.m, which gives rise to variation of characteristics of the elements, and may cause a great disadvantage practically.
For example, a field-effect transistor, provided on the above-mentioned polycrystalline Si layer comprising large grains on a 4-inch substrate, exhibits variation of the electron mobility of 110 cm.sup.2 /v.sec relative to 110 cm.sup.2 /v.sec and variation of the threshold value of .+-.0.5 v, which variations are significantly larger than those of the transistor provided on a single crystal Si substrate, causing a large obstruction in constructing an integrated circuit.
(4) Donor-acceptor impurities which modify electrical properties generally such as P, B, As, etc. are known to affect the growth of Si crystal. In particular, P is known to promote abnormal grain growth. (Y. Wada & S. Nishimatsu, J. Electrochem. Soc, Vol. 125, No. 9, p 1499)
The inventors of the present invention, however, after long period of comprehensive study on every kind of impurity, have found that the aforementioned donor-acceptor impurities accelerate crystallization only when the impurity is introduced in a large amount near to the solid-solubility limit, and in that case an n.sup.+ or p.sup.+ layer is formed which is unsuitable for an active semiconductor, layer, making difficult the preparation of elements.